1. Field of the Invention
The present invention generally relates to a thin film magnetic memory device. More particularly, the present invention relates to a random access memory (RAM) including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device capable of non-volatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the use of thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells significantly improves performance of the MRAM device. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000, and xe2x80x9cA 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAMxe2x80x9d, ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 39 schematically shows the structure of a memory cell having a magnetic tunnel junction (hereinafter, sometimes simply referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 39, the MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance varying according to the storage data level, and an access element ATR for forming a path of a sense current Is flowing through tunneling magneto-resistance element TMR in data read operation. Since a field effect transistor is typically used as access element ATR, access element ATR is hereinafter sometimes referred to as access transistor ATR. Access transistor ATR is coupled between tunneling magneto-resistance element TMR and a fixed voltage (ground voltage GND).
A write word line WWL for data write operation, a read word line RWL for data read operation, and a bit line BL are provided for the MTJ memory cell. Bit line BL serves as a data line for transmitting an electric signal corresponding to the storage data level in data read operation and data write operation.
FIG. 40 is a conceptual diagram illustrating data read operation from the MTJ memory cell.
Referring to FIG. 40, tunneling magneto-resistance element TMR has a ferromagnetic material layer FL having a fixed magnetization direction (hereinafter, sometimes simply referred to as xe2x80x9cfixed magnetic layerxe2x80x9d), a ferromagnetic material layer VL that is magnetized in the direction according to an external magnetic field (hereinafter, sometimes simply referred to as xe2x80x9cfree magnetic layerxe2x80x9d), and an antiferromagnetic material layer AFL for fixing the magnetization direction of fixed magnetic layer FL. A tunneling barrier (tunneling film) TB of an insulator film is interposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized either in the same (parallel) direction as, or in the opposite (antiparallel) direction to, that of fixed magnetic layer FL according to the write data level. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
In data read operation, access transistor ATR is turned ON in response to activation of read word line RWL. This allows a sense current Is to flow through a current path formed by bit line BL, tunneling magneto-resistance element TMR, access transistor ATR and ground voltage GND.
The electric resistance of tunneling magneto-resistance element TMR varies according to the relation between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. More specifically, when fixed magnetic layer FL and free magnetic layer VL have the same (parallel) magnetization direction, tunneling magneto-resistance element TMR has a smaller electric resistance than that of the case where they have opposite (antiparallel) magnetization directions.
Accordingly, when free magnetic layer VL is magnetized in the direction according to the storage data level, a voltage change produced on tunneling magneto-resistance element TMR by sense current Is varies depending on the storage data level. Therefore, by precharging bit lines BL to a prescribed voltage and then applying sense current Is to tunneling magneto-resistance element TMR, the storage data of the MTJ memory cell can be read by sensing the voltage on bit line BL.
FIG. 41 is a conceptual diagram illustrating data write operation to the MTJ memory cell.
Referring to FIG. 41, in data write operation, read word line RWL is inactivated and access transistor ATR is turned OFF. In this state, a data write current is applied to write word line WWL and bit line BL in order to magnetize free magnetic layer VL in the direction according to the write data level. The magnetization direction of free magnetic layer VL is determined by combination of the directions of the data write currents flowing through write word line WWL and bit line BL.
FIG. 42 is a conceptual diagram illustrating the relation between the data write current and the magnetization direction of the tunneling magneto-resistance element in data write operation to the MTJ memory cell.
Referring to FIG. 42, the abscissa H(EA) indicates a magnetic field that is applied to free magnetic layer VL of tunneling magneto-resistance element TMR in the easy-axis (EA) direction. The ordinate H(HA) indicates a magnetic field that is applied to free magnetic layer VL in the hard-axis (HA) direction. Magnetic fields H(EA), H(HA) respectively correspond to two magnetic fields produced by the currents flowing through bit line BL and write word line WWL.
In the MTJ memory cell, fixed magnetic layer FL is magnetized in the fixed direction along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized either in the direction parallel or antiparallel (opposite) to that of fixed magnetic layer FL along the easy axis according to the storage data level (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d). Hereinafter, R1 and R0 (where R1 greater than R0) denote the electric resistances of tunneling magneto-resistance element TMR corresponding to the two magnetization directions of free magnetic layer VL.
The MTJ memory cell is thus capable of storing 1-bit data (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) according to the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when the sum of the applied magnetic fields H(EA) and H(HA) reaches the region outside the asteroid characteristic line in FIG. 42. In other words, the magnetization direction of free magnetic layer VL will not change if an applied data write magnetic field corresponds to the region inside the asteroid characteristic line.
As shown by the asteroid characteristic line, applying a magnetic field of the hard-axis direction to free magnetic layer VL enables reduction in magnetization threshold value required to change the magnetization direction along the easy axis.
When the write operation point is designed as in the example of FIG. 42, a data write magnetic field of the easy-axis direction is designed to have strength HWR in the MTJ memory cell to be written. In other words, a data write current to be applied to bit line BL or write word line WWL is designed to produce data write magnetic field HWR. Data write magnetic field HWR is commonly defined by the sum of a switching magnetic field HSW required to switch the magnetization direction and a margin xcex94H. Data write magnetic field HWR is thus defined by HWR=HSW+xcex94H.
In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of tunneling magneto-resistance element TMR, a data write current of at least a prescribed level must be applied to both write word line WWL and bit line BL. Free magnetic layer VL in tunneling magneto-resistance element TMR is thus magnetized in the direction parallel or antiparallel (opposite) to that of fixed magnetic layer FL according to the direction of the data write magnetic field along the easy axis (EA). The magnetization direction written to tunneling magneto-resistance element TMR, i.e., the storage data of the MTJ memory cell, is held in a non-volatile manner until another data write operation is conducted.
As described above, the electric resistance of tunneling magneto-resistance element TMR varies according to the magnetization direction that is rewritable by an applied data write magnetic field. Accordingly, non-volatile data storage can be realized by using the two magnetization directions of free magnetic layer VL in tunneling magneto-resistance element TMR as storage data levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d), respectively.
When the MRAM device integrates such MTJ memory cells, the MTJ memory cells are commonly arranged in a matrix on a semiconductor substrate.
FIG. 43 is a conceptual diagram showing the array structure of the MTJ memory cells arranged in a matrix in an integrated manner.
In FIG. 43, the MTJ memory cells are arranged in n rows by m columns (where n, m is a natural number). As described before, bit line BL, write word line WWL and read word line RWL need be provided for each MTJ memory cell.
In data write operation, a prescribed data write current is applied to a write word line WWL and a bit line BL corresponding to the selected memory cell. For example, when the data is to be written to the shaded MTJ memory cell in FIG. 43, a data write current Ip of the row direction is applied to write word line WWL6, and a data write current Iw of the column direction is applied to bit line BL2. Accordingly, the selected MTJ memory cell receives both a data write magnetic field H(EA) of the easy-axis direction and a data write magnetic field H(HA) of the hard-axis direction beyond switching magnetic field HSW of FIG. 42. As a result, free magnetic layer VL is magnetized in the direction according to the write data level.
On the other hand, the non-selected memory cells of the same memory cell row and the same memory cell column as that of the selected memory cell (in the example of FIG. 43, the non-selected memory cells corresponding to write word line WWL6 and the non-selected memory cells corresponding to bit line BL2) receive only one of data write magnetic field H(EA) of the easy-axis direction and data write magnetic field H(HA) of the hard-axis direction beyond switching magnetic filed HSW. In these memory cells, the magnetization direction of free magnetic layer VL will not be rewritten. In other words, data write operation will not be conducted theoretically.
If a magnetic noise of the other direction is applied to the above non-selected memory cells, however, data may be erroneously written thereto.
A typical example of such a magnetic noise is a magnetic field generated by a current flowing through a power supply voltage line and a ground line for supplying an operating voltage to the peripheral circuitry for conducting data read operation and data write operation from and to the memory array. The current flowing through the power supply voltage line and the ground line are likely to reach a peak during operation of the peripheral circuitry. Therefore, the magnetic noise from these power supply lines has a certain level of intensity.
Especially for improved integration, these power supply lines may be provided near the memory array, that is, near tunneling magneto-resistance elements TMR. In this case, the magnetic noise from the power supply lines may cause a reduced operation margin and erroneous writing. Therefore, such problems must be prevented in some way.
It is an object of the present invention to enables stable operation of a thin film magnetic memory device by suppressing the influences of magnetic noises from power supply lines provided for peripheral circuitry and the like, more specifically, magnetic noises from a power supply voltage line and a ground line.
In summary, according to one aspect of the present invention, a thin film magnetic memory device includes a memory array, a peripheral circuitry, and first and second power supply lines. The memory array has a plurality of memory cells for magnetic data storage arranged therein. Each memory cell includes a magnetic storage portion having an electric resistance varying according to a magnetization direction that is rewritable by application of a prescribed magnetic field. The peripheral circuitry is provided in a region adjacent to the memory array, and conducts data read operation and data write operation from and to the memory array. The first and second power supply lines supply an operating voltage to the peripheral circuitry. The first and second power supply lines are arranged so that a magnetic field generated by a current flowing through the first power supply line and a magnetic field generated by a current flowing through the second power supply line cancel each other in the memory array.
According to another aspect of the present invention, a thin film magnetic memory device includes a memory array, a peripheral circuitry, and first and second power supply lines. The memory array has a plurality of memory cells for magnetic data storage arranged therein. Each memory cell includes a magnetic storage portion having an electric resistance varying according to a magnetization direction that is rewritable by application of a prescribed magnetic field. The peripheral circuitry is provided in a region adjacent to the memory array, and conducts data read operation and data write operation from and to the memory array. The first and second power supply lines supply an operating voltage to the peripheral circuitry. The first and second power supply lines are arranged so that a first magnetic field generated by a current flowing through the first power supply line and a second magnetic field generated by a current flowing through the second power supply line are applied to the memory array in an easy-axis (EA) direction of the magnetic storage portions.
According to still another aspect of the present invention, a thin film magnetic memory device includes a memory array, a peripheral circuitry, and first and second power supply lines. The memory array has a plurality of memory cells for magnetic data storage arranged therein. Each memory cell includes a magnetic storage portion having an electric resistance varying according to a magnetization direction that is rewritable by application of a prescribed magnetic field. The peripheral circuitry is provided in a region adjacent to the memory array, for conducting data read operation and data write operation from and to the memory array. The first and second power supply lines supply an operating voltage to the peripheral circuitry. Each of the first and second power supply lines is provided at least at a prescribed distance away from the magnetic storage portion of a nearest one of the memory cells so that a peak magnetic field generated by a peak current flowing therethrough has a strength smaller than a prescribed value in the magnetic storage portion of the nearest memory cell. The prescribed value is determined in view of magnetization characteristics of the memory cells.
According to yet another aspect of the present invention, a thin film magnetic memory device includes a memory array, a peripheral circuitry, a power supply node, a power supply line, and a decoupling capacitor. The memory array has a plurality of memory cells for magnetic data storage arranged therein. Each memory cell includes a magnetic storage portion having an electric resistance varying according to a magnetization direction that is rewritable by application of a magnetic field. The peripheral circuitry is provided in a region adjacent to the memory array, and conducts data read operation and data write operation from and to the memory array. The power supply node faces the peripheral circuitry in a first direction with the memory array interposed therebetween, and receives an operating power supply voltage of the peripheral circuitry. The power supply line extends between the power supply node and the peripheral circuitry in the first direction, and transmits the operating power supply voltage. The decoupling capacitor is provided between the power supply line and a ground voltage in at least one of a region between the power supply node and the memory array and a region between the peripheral circuitry and the memory array.
According to a further aspect of the present invention, a thin film magnetic memory device includes a memory array and a plurality of dummy magnetic elements. The memory array has a plurality of memory cells for magnetic data storage arranged in a matrix. The plurality of dummy magnetic elements are provided at an end of the memory array along at least one of memory cell rows and memory cell columns, and having a fixed magnetization direction.
According to a still further aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of first wirings, and an inductance element. The memory array has a plurality of memory cells for magnetic data storage arranged therein, and each memory cell includes a first magnetic element. The plurality of first wirings are provided for the memory array. Each first wiring is electrically connected to the first magnetic element included in at least one of the plurality of memory cells. The inductance element includes a second wiring formed in a same wiring layer as that of the plurality of first wirings in a region outside the memory array, and a second magnetic element formed in a same layer as that of the first magnetic elements in the region outside the memory array and electrically connected to the second wiring.
According to a yet further aspect of the present invention, a thin film magnetic memory device includes a plurality of memory cells, a first wiring, and a second wiring. The plurality of memory cells are arranged in a matrix for magnetic data storage. The first wiring applies a write magnetic field to a memory cell selected for data write operation. The second wiring is provided farther away from the plurality of memory cells than is the first wiring, and supplies to the first wiring a write current for generating the write magnetic field. In the data write operation, magnetic fields generated from the first and second wirings cancel each other in at least a part of a region along a longitudinal direction of the first and second wirings.
According to a yet further aspect of the present invention, a thin film magnetic memory device includes a plurality of memory cells for magnetic data storage, a plurality of peripheral circuitries, and a plurality of power supply lines. The plurality of memory cells is divided into a plurality of banks. The plurality of banks are selectively written in each write operation. The plurality of peripheral circuitries are provided corresponding to the plurality of banks. Each peripheral circuitry conducts at least data write operation to a corresponding bank. The plurality of power supply lines are provided corresponding to the plurality of peripheral circuitries. Each power supply line supplies an operating voltage to a corresponding peripheral circuitry. Each power supply line is provided in a region corresponding to at least one of banks other than a corresponding bank and a bank that may be written simultaneously with the corresponding bank.
According to a yet further aspect of the present invention, a thin film magnetic memory device includes a plurality of memory cells, a plurality of first write lines, a plurality of second write lines, and a plurality of wirings. The plurality of memory cells are arranged in a matrix for magnetic data storage. The plurality of first write lines are provided corresponding to one of memory cell rows and memory cell columns, and selectively receive a data write current in order to mainly apply a magnetic field of an easy-axis direction to a selected memory cell. The plurality of second write lines are provided corresponding to the other of the memory cell rows and the memory cell columns, and selectively receive a data write current in order to mainly apply a magnetic field of a hard-axis direction to the selected memory cell. The plurality of wirings are formed from an electrically conductive material. A residual magnetic field margin along the easy-axis direction and a residual magnetic field margin along the hard-axis direction have different values when the memory cell is subjected to both a magnetic field noise generated from a nearest one of the first write lines other than the corresponding first write line and a magnetic field noise generated from a nearest one of the second write lines other than the corresponding second write line. One of the plurality of wirings that is located nearest to the memory cells extends in such a direction that a magnetic field generated by a current flowing therethrough mainly has in the memory cells a component along either the easy-axis direction or the hard-axis direction which corresponds to a greater magnetic field residual margin.
According to a yet further aspect of the present invention, a thin film magnetic memory device includes a plurality of memory cells, a plurality of first write lines, a plurality of second write lines, and a power supply line. The plurality of memory cells are arranged in a matrix for magnetic data storage. The plurality of first write lines are provided corresponding to one of memory cell rows and memory cell columns, and selectively receive a data write current in order to mainly apply a magnetic field of an easy-axis direction to a selected memory cell. The plurality of second write lines are provided corresponding to the other of the memory cell rows and the memory cell columns, and selectively receive a data write current in order to mainly apply a magnetic field of a hard-axis direction to the selected memory cell. The power supply line is included in a path of the data write current. A residual magnetic field margin along the easy-axis direction and a residual magnetic field margin along the hard-axis direction have different values when the memory cell is subjected to both a magnetic field noise generated from a nearest one of the first write lines other than the corresponding first write line and a magnetic field noise generated from a nearest one of the second write lines other than the corresponding second write line. The power supply line extends in such a direction that a magnetic field generated by a current flowing therethrough mainly has in the memory cells a component along either the easy-axis direction or the hard-axis direction which corresponds to a greater residual margin.
Accordingly, a main advantage of the present invention is as follows: since the magnetic fields generated by the first and second power supply lines cancel each other in the memory array, erroneous writing and reduced operation margin caused by the magnetic noises from the power supply lines can be prevented, whereby stable operation is achieved.
The magnetic noises from the power supply lines can be applied to the memory array in the easy-axis direction of the magnetic storage portions (tunneling magneto-resistance elements). This suppresses the magnetic noise of the hard-axis direction to the non-selected memory cell group of the selected column, thereby preventing erroneous writing caused by the magnetic noises generated from the power supply lines in data write operation. In the operation other than data write operation as well, magnetic noises that rotate the magnetization direction of the magnetic storage portions (tunneling magneto-resistance elements) will not be applied to the memory cells. This prevents reduction in read operation margin caused by the magnetic noises from the power supply lines.
The magnetic noise from each power supply line has a peak strength smaller than a prescribed value in the memory cell located nearest to the power supply line, and the prescribed value is determined in view of magnetization characteristics of the memory cells. As a result, the operation stability will not be impeded by the magnetic noises from the power supply lines.
The decoupling capacitor receiving a peak current is provided on a region of the power supply line other than a region near the memory array. Such efficient arrangement of the decoupling capacitor enables suppression of the magnetic noises from the power supply lines.
Moreover, the dummy magneto-resistance elements provided at the end of the memory array prevent the magnetic field from becoming discontinuous at the end of the memory array. Therefore, the operation margin of the memory cells arranged at the end region of the memory array will not be degraded.
The inductance element can be formed using a magnetic element capable of being manufactured simultaneously with the memory cells in the manufacturing process of the memory cells. As a result, the inductance element can be fabricated without increasing the number of steps in the manufacturing process.
A magnetic noise from the first wiring (which corresponds to a leak magnetic filed of the write magnetic filed) and a magnetic noise from the second wiring included in the path of the write current cancel each other in the non-selected memory cells. This reduces the magnetic noises to the non-selected memory cells, thereby improving operation reliability of the thin film magnetic memory device.
When the memory cells are divided into a plurality of banks that are selectively written in data write operation (i.e., the plurality of banks will not be simultaneously selected for data write operation), erroneous writing to the non-selected memory cells is prevented from occurring in the data write operation. As a result, operation reliability of the thin film magnetic memory device is improved.
The non-selected memory cells located near the selected memory cell are most likely to be subjected to erroneous writing of the data. Therefore, one of the wirings other than the write lines which is located nearest to the memory cells extends in such a direction that the nearest wiring applies to these non-selected memory cells a magnetic noise having the same direction as that of a relatively large margin for erroneous writing. This prevents erroneous writing to the non-selected memory cells from occurring in data write operation, whereby operation reliability of the thin film magnetic memory device is improved.
As described above, the non-selected memory cells located near the selected memory cell are most likely to be subjected to erroneous writing of the data. Therefore, a power supply line receiving a relatively large current extends in such a direction that it applies to these non-selected memory cells a magnetic noise having the same direction as that of a relatively large margin for erroneous writing. This prevents erroneous writing to the non-selected memory cells from occurring in data write operation, whereby operation reliability of the thin film magnetic memory device is improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.